I’m going to remove the conditional code, since it just complicates things:<\/p>\n
\/\/ Runtime Interrupt Vectors\n\/\/ -------------------------\nVectors:\n b _start \/\/ reset - _start\n ldr pc,_undf \/\/ undefined - _undf\n ldr pc,_swi \/\/ SWI - _swi\n ldr pc,_pabt \/\/ program abort - _pabt\n ldr pc,_dabt \/\/ data abort - _dabt\n nop \/\/ reserved\n ldr pc,[pc,#-0xFF0] \/\/ IRQ - read the VIC\n ldr pc,_fiq \/\/ FIQ - _fiq\n\n_undf: .word __undf \/\/ undefined\n_swi: .word __swi \/\/ SWI\n_pabt: .word __pabt \/\/ program abort\n_dabt: .word __dabt \/\/ data abort\n_irq: .word __irq \/\/ IRQ\n_fiq: .word __fiq \/\/ FIQ\n\n__undf: b . \/\/ undefined\n__swi: b . \/\/ SWI\n__pabt: b . \/\/ program abort\n__dabt: b . \/\/ data abort\n__irq: b . \/\/ IRQ\n__fiq: b . \/\/ FIQ\n\n .size _boot, . - _boot\n .endfunc\n<\/code><\/pre>\nLets look first at the reset\/start vector:<\/p>\n
b _start\n<\/code><\/pre>\nThat instruction is an unconditional branch (a jump) to the the code labeled “_start” which I don’t see in your snippet. Basically it’ll be the assembly that initializes the stack and processor registers, maybe some memory areas then probably jumps to a C routine that performs the bulk of the initialization.<\/p>\n
Next is the “undefined” vector that the ARM will go to when an invalid instruction is executed (if my memory is right):<\/p>\n
ldr pc, _undf\n<\/code><\/pre>\nThat instruction loads the pc<\/code> register (the ‘program counter’ or instruction pointer) with the address at the “_undf” symbol. If we look at the _undf<\/code> variable, it contains the address represented by symbol __undf<\/code>. So the ldr pc, _undf<\/code> instruction loads pc<\/code> with __undf<\/code>‘s address – jumping to __undf:<\/code>.<\/p>\nAnd at __undf<\/code> we see:<\/p>\n__undf: b . \n<\/code><\/pre>\nThat’s just a branch to the same address – an infinite loop (the .<\/code> symbol means ‘here’ or ‘this location’).<\/p>\nSo for most of these vectors (which follow the same technique as the undefined vector), they’ll just jump to little infinite loops. You could replace the infinite loops at those labels with code that’s appropriate for the vector in question, though many projects don’t because those vectors firing would represent some sort of serious error.<\/p>\n
Finally, the vector slot that’s most interesting is the IRQ vector:<\/p>\n
ldr pc,[pc,#-0xFF0] \/\/ IRQ - read the VIC\n<\/code><\/pre>\nThis looks like the handler for an NXP device.<\/p>\n
It loads the pc<\/code> register with the value read from a memory location that’s relative to the pc<\/code> register. Since on the ARM architecture the IRQ vector is always<\/em> at address 0x00000018 (I’m going to ignore implementations that can map the vectors elsewhere or ARMs like the Cortex-M3 that use a different vector model) and because of the instruction pipeline’s effect on using the PC<\/code> register value for addressing, the memory location that will be read by this instruction will be 0xFFFFF030<\/code>, which is the address of the memory-mapped VICVectAddr<\/code> register in the ‘Vectored Interrupt Controller` (VIC):<\/p>\n 'apparent' Pipeline offset in effective\n PC value effect the opcode address\n------------- ------------ ----------- ----------\n 0x00000018 + 0x00000008 - 0x0000ff0 == 0xfffff030\n<\/code><\/pre>\nThis device register will contain the address of the interrupt handler for the interrupt that just occurred (of course the VIC needs to be properly initialized so it knows that address).<\/p>\n
So when the ldr pc,[pc,#-0xFF0]<\/code> instruction executes, it’ll load the pc<\/code> register with the address of the interrupt handler routine for the appropriate device (basically, jumping to the right interrupt handler).<\/p>\nOriginally posted 2013-11-09 22:51:02. <\/small><\/p>","protected":false},"excerpt":{"rendered":"
I’m going to remove the conditional code, since it just complicates things: \/\/ Runtime Interrupt Vectors \/\/ ————————- Vectors: b _start \/\/ reset – _start ldr pc,_undf \/\/ undefined – _undf ldr pc,_swi \/\/ SWI – _swi ldr pc,_pabt \/\/ program abort – _pabt ldr pc,_dabt \/\/ data abort – _dabt nop \/\/ reserved ldr […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-874","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"https:\/\/unknownerror.org\/index.php\/wp-json\/wp\/v2\/posts\/874","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/unknownerror.org\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/unknownerror.org\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/unknownerror.org\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/unknownerror.org\/index.php\/wp-json\/wp\/v2\/comments?post=874"}],"version-history":[{"count":0,"href":"https:\/\/unknownerror.org\/index.php\/wp-json\/wp\/v2\/posts\/874\/revisions"}],"wp:attachment":[{"href":"https:\/\/unknownerror.org\/index.php\/wp-json\/wp\/v2\/media?parent=874"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/unknownerror.org\/index.php\/wp-json\/wp\/v2\/categories?post=874"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/unknownerror.org\/index.php\/wp-json\/wp\/v2\/tags?post=874"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}